1. Field of the Invention
This invention relates to interconnecting multiple metal wiring levels of integrated circuit structures by the formation of conductive plugs through a plurality of insulation layers. More particularly, this invention relates to the formation of openings through multiple layers of insulation to electrically connect portions of one metal wiring layer with portions of another metal wiring layer using a via etch mask located between the insulation layers.
2. Description of the Related Art
The forming of electrical connections between metal wiring on one level in an integrated circuit structure with metal wiring on a different level is usually accomplished by forming a vertical opening known as a via through one or more layers of insulation which separate the two levels of metal wiring.
This is normally carried out by forming one or more insulation layers over the first metal wiring level, masking the one or more insulation layers with a via etch mask, and then selectively etching the layer or insulation layers through openings in the via etch mask down to the underlying metal wiring to form the vias. The vias are then filled with metal, either in an independent step or during the deposition of a further metal layer, followed by patterning of the deposited metal layer, using a reverse metal wiring mask (a mask with solid portions corresponding to the desired metal wiring), to form the second metal wiring level.
There are several problems with this conventional method of forming vias and using these vias to electrically connect multiple metal wiring levels. The vias are not self-aligned and some overlap of the metal above and below the via is needed. Furthermore, separate etch masks and etch steps are required to respectively form the vias (by etching the underlying insulation layer through a via etch mask) and to later pattern the subsequently deposited metal layer. Also, when the via is filled the same metal which later will be patterned, only one layer can be filled by flowing the metal into the via, since heating the additional layers would melt the metal underneath and deform the metal lines. Furthermore, when a generic gate array structure is initially formed which will later have either contact openings formed to the substrate or vias formed down to a lower metal wiring layer, additional masks and processing steps are involved when the vias must be later formed as a part of a custom wiring structure to only contact selected underlying devices, e.g., certain MOS transistors in the underlying gate array of MOS transistors.